Plasma processing system ESC high voltage control

ABSTRACT

A plasma processing system is disclosed. The plasma processing system may include an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support a wafer. The ESC may include a positive terminal (+ESC) for providing a first force to the wafer and a negative terminal (−ESC) for providing a second force to the wafer. The plasma processing system may also include a first trans-impedance amplifier (TIA) and a second TIA configured to measure a first set of voltages for calculating a value of a positive load current applied to the positive terminal. The plasma processing system may also include a third TIA and a fourth TIA configured to measure a second set of voltages for calculating a value of a negative load current applied to the negative terminal.

RELATED APPLICATIONS

This application claims the benefit under 35 USC 119(e) of ProvisionalApplication No. 60/941,642, filed on Jun. 1, 2007 by inventors SeyedJafar Jafarian-Tehrani and Ralph Jan-Pin Lu.

BACKGROUND OF THE INVENTION

In the semiconductor industry, a plasma processing system may beutilized to perform processing (e.g., etching or deposition) on wafers.In general, a wafer may be secured on an electrostatic chuck (ESC) byelectrostatic forces for the processing. In order to ensure the wafer isstable during the processing, the electrostatic forces applied on thewafer by the positive and negative terminals of the ESC may need to bebalanced by adjusting power supply. To adjust the power supply, thevalues of the positive load current supply to the positive terminal andthe negative load current supply to the negative terminal may need to becalculated or measured.

FIG. 1A illustrates a schematic representation of an example plasmaprocessing system 160. Plasma processing system 160 may include achamber 169. Inside the chamber there may be an electrostatic chuck 164for supporting wafers, such as wafer 162, during processing utilizingplasma 179. Plasma processing system 160 may have a DC power supply 166to provide the clamping voltage 172 for securing wafer 162 on chuck 164.The DC power supply may be programmable, e.g., utilizing a bias controlor sensor input 198 and/or a clamp control 197, for setting a biasvoltage 170 that defines a center of the clamping voltage 172, which maybe a voltage with two endpoints, e.g., positive high voltage (+HV) 129and negative high voltage (−HV) 130 (also illustrated in the example ofFIG. 1B).

In order to keep the wafer 162 secured, or “clamped”, on theelectrostatic chuck 164 it may be required to tune bias voltage 170 fora condition such that bias voltage 170 matches a plasma induced biasvoltage 194 across chuck 164; plasma induced bias voltage 194 may not bedirectly measured/adjusted. The required condition may be equivalent toa condition that the value of the positive load current 181 applied topositive terminal 185 is substantially equal to the value of negativeload current 182 applied to negative terminal 186. If the values of theload current are substantially different, electrostatic forces suppliedby positive terminal 185 and negative terminal 186 may be substantiallydifferent, and wafer 162 may be tilted. As a result, the yield of plasmaprocessing may be reduced.

In order to ensure the values of the load currents are substantiallyequal, the values may need to be measured, sampled and/or calculated.

FIG. 1B illustrates a schematic representation of a prior artarrangement including an isolation amplifier 132 for measuring the valueof positive load current 181 illustrated in the example of FIG. 1A. Asimilar arrangement may be made for measuring the value of negative loadcurrent 182 illustrated in the example of FIG. 1A.

In the prior art arrangement, with reference to FIG. 1A-B, DC powersupply 166 may supply positive high voltage 129, e.g., with a value of2000 V, into plasma processing chamber 169 through RF filter 187 andpositive terminal 185; RF filter 187 and positive terminal 185 may berepresented by an equivalent resistor 107. The arrangement may include asensing resistance 100 disposed between a first terminal 151 and asecond terminal 152, first terminal 151 and second terminal 152 may bedisposed between a terminal of DC power supply 166 with positive highvoltage (+HV) 129 and equivalent resistor 107.

The arrangement may also include an instrumentation amplifier 102electrically coupled with first terminal 151 and second terminal 152through resistor 117 and resistor 118, respectively. Instrumentation 102may be configured to sense the voltage between first terminal 151 andsecond terminal 152, i.e., ΔV 171, in order to determine the value ofsensing current 103 utilizing the resistance value of sensing resistor100.

In order for instrumentation amplifier 102 to sense ΔV 171, isolationamplifier 132 may be employed to shift the operating point (or operatingrange) of instrumentation amplifier 102 up, for example, to a range ofabout 2000V−15V˜about 2000V+15V. Having a high operating point,instrumentation amplifier 102 may be able to sense ΔV 171.

Typical equipment for measuring voltage may only be able to measurevoltages in a range of about −15V˜about +15V. In order to obtain, thevalue of a high voltage output 116 of instrumentation amplifier 102,isolation amplifier 132 may also be configured to shift output 116 to alow voltage referenced output 134 that is within a range of −15V˜+15Vrelative to ground level 136. Low voltage referenced output 134 may bemeasured utilizing typical voltage measurement equipment. Subsequently,low voltage referenced output 134 may be utilized to calculate output116. In turn, output 116 may be utilized to determine the value of ΔV171, which may be utilized to determine the value of sensing current103. The value of positive load current 181 may be assumed to be equalto the value of sensing current 103 according to the prior artarrangement.

In general, isolation amplifier 132 may be very expensive. Further, thecapability of isolation amplifier 132 may be substantially limited.Typically, isolation amplifier 132 may only be able to shift theoperating point of instrumentation amplifier 102 up to about 2.5 kV. Thelimitation may be insufficient to satisfy requirements of some plasmaprocessing systems, which may have a high voltage input of about 6 kV oreven higher.

Instrumentation amplifier 102 also may have limitations. For example,instrumentation amplifier 102 typically may have a sensing range of onlyfrom −10V˜+10V. Given such limitations, instrumentation amplifier 102may not be able to satisfy the requirements of some plasma processingsystems.

SUMMARY

An embodiment of the invention relates to a plasma processing system.The plasma processing system may include an electrostatic chuck (ESC)positioned inside a plasma processing chamber and configured to support(and clamp) a wafer. The ESC may include a positive terminal (+ESC) forproviding a first force to the wafer and a negative terminal (−ESC) forproviding a second force to the wafer. The plasma processing system mayalso include a first trans-impedance amplifier (TIA) and a second TIAconfigured to measure a first set of voltages for calculating a value ofa positive load current applied to the positive terminal. The plasmaprocessing system may also include a third TIA and a fourth TIAconfigured to measure a second set of voltages for calculating ormeasuring a value of a negative load current applied to the negativeterminal. The plasma processing system may also include logic or aprogram for adjusting a bias voltage such that the value of the positiveload current and the value of the negative load current may have anequal magnitude. The plasma processing system may also include adiagnostic unit configured to determine at least one of a healthcondition and a remaining life of the ESC based on at least one of thevalue of the positive load current and the value of the negative loadcurrent.

The above summary relates to only one of the many embodiments of theinvention disclosed herein and is not intended to limit the scope of theinvention, which is set forth in the claims herein. These and otherfeatures of the present invention will be described in more detail belowin the detailed description of the invention and in conjunction with thefollowing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1A illustrates a schematic representation of an example plasmaprocessing system.

FIG. 1B illustrates a schematic representation of a prior artarrangement including an isolation amplifier for measuring the value ofa positive load current in plasma processing system illustrated in theexample of FIG. 1A.

FIG. 2A illustrates a schematic representation of an arrangement formeasuring a value/amperage of a positive load current applied to apositive terminal of an electrostatic chuck in a plasma processingsystem in accordance with one or more embodiments of the invention.

FIG. 2B illustrates a flowchart of a method for obtaining thevalue/amperage of the positive load current in accordance with one ormore embodiments of the present invention.

FIG. 2C illustrates a mathematical manipulation for obtaining thevalue/amperage of the positive load current.

FIG. 3 illustrates a schematic representation of an arrangement forobtaining a value/amperage of a negative load current applied to anegative terminal of the electrostatic chuck in the plasma processingsystem discussed in the example of FIG. 2A-C in accordance with one ormore embodiments of the present invention.

FIG. 4 illustrates a positive load current plot and a negative loadcurrent plot for optimizing a bias voltage in the plasma processingsystem discussed in FIGS. 2A-C and FIG. 3 in accordance with one or moreembodiments of the present invention.

DETAILED DESCRIPTION

The present invention will now be described in detail with reference toa few embodiments thereof as illustrated in the accompanying drawings.In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Itwill be apparent, however, to one skilled in the art, that the presentinvention may be practiced without some or all of these specificdetails. In other instances, well known process steps and/or structureshave not been described in detail in order to not unnecessarily obscurethe present invention.

One or more embodiments of the invention relate to a plasma processingsystem. The plasma processing system may include an electrostatic chuck(ESC) positioned inside a plasma processing chamber and configured tosupport a wafer. The ESC may include a positive terminal (+ESC) forproviding a first force to the wafer and a negative terminal (−ESC) forproviding a second force to the wafer. The high voltages on a positiveterminal (+ESC) and negative terminal (−ESC) may be programmable andcontrolled.

The plasma processing system may also include a first trans-impedanceamplifier (TIA) and a second TIA configured to measure a first set ofvoltages for calculating a value of a positive load current applied tothe positive terminal. The plasma processing system may also include athird TIA and a fourth TIA configured to measure a second set ofvoltages for calculating a value of a negative load current applied tothe negative terminal.

The plasma processing system may also include logic or a program (e.g.,included in a bias control/sensor input unit similar to bias control orsensor input 198 illustrated in the example of FIG. 1A) for adjusting abias voltage such that the value of the positive load current and thevalue of the negative load current may have an equal magnitude or mayhave an offset that corrects an error of an estimated plasma inducedbias voltage. Accordingly, the first force and the second force may bebalanced, and the wafer may be secured on the ESC.

The plasma processing system may also include a diagnostic unit (e.g.,included in a bias control/sensor input unit similar to bias control orsensor input 198 illustrated in the example of FIG. 1A) configured todetermine at least one of a health condition and a remaining life of theESC based on at least one of the value of the positive load current andthe value of the negative load current.

The plasma processing system may also include a control unit. Thecontrol unit may be configured to control at least a first ESC voltageat the positive terminal and a second ESC voltage at the negativeterminal using at least one of a first voltage measured by the secondTIA and a second voltage measured by the fourth TIA. The first ESCvoltage may be proportional to the first voltage; the second ESC voltagemay be proportional to the second voltage. Accordingly, the highvoltages at the positive and negative terminals may follow (or track)programmable input set-points, independent of other process variables orenvironmental variables.

The first ESC voltage may be positive, and the second ESC voltage may benegative. In one or more embodiments, for example, when the polaritiesof the positive terminal and the negative terminals are reversed, thefirst ESC voltage may be negative, and the second ESC voltage may bepositive.

The control unit may also be configured to control the differencebetween the first ESC voltage and the second ESC voltage. The differencemay represent a clamp voltage pertaining to clamping forces applied onthe wafer.

One or more embodiments of the invention relate to a method for securinga wafer on an electrostatic chuck (ESC) positioned inside a plasmaprocessing chamber. The ESC may include a positive terminal forproviding a first force to the wafer and a negative terminal forproviding a second force to the wafer. The method may includeconnecting, using a first component, a first trans-impedance amplifier(TIA) to a first terminal on a first electrical path. The firstelectrical path may be between a power supply and the positive terminal.The first component may have a first resistance. The method may alsoinclude determining, using the first TIA, a first voltage across asecond component. The second component may connect two end points of thefirst TIA and may have a second resistance;

The method may also include connecting, using a third component, asecond TIA to a second terminal on the first electrical path. The thirdcomponent may have a third resistance. The method may also includedetermining, using the second TIA, a second voltage across a fourthcomponent. The fourth component may connect two end points of the secondTIA and may have a fourth resistance.

The method may also include determining a value of a positive loadcurrent applied to the positive terminal using one or more of the firstvoltage, the first resistance, the second resistance, the secondvoltage, the third resistance, and the fourth resistance. The method mayalso include determining a value of a negative load current applied tothe negative terminal. The method may also include adjusting a biasvoltage using the value of the positive load current and the value ofthe negative load current for balancing the first force and the secondforce.

The method may also include converting a ratio of the first resistanceto the second resistance into a product of at least a first intermediateterm and a second intermediate term. The method may also includecalculating an intermediate voltage term using the first voltage, thesecond voltage, and the first intermediate term. The method may alsoinclude calculating an inter-terminal voltage between the first terminaland the second terminal using the intermediate voltage term, the secondintermediate term, the second voltage, the second resistance, and aninter-terminal resistance between the first terminal and the secondterminal.

The step of determining the value of the positive load current mayinclude determining, using the first voltage, the first resistance, andthe second resistance, a first terminal voltage at the first terminal.The step of determining the value of the positive load current may alsoinclude determining, using the second voltage, the third resistance, andthe fourth resistance, a second terminal voltage at the second terminal.

The step of determining the value of the positive load current may alsoinclude determining, using the first terminal voltage, the secondterminal voltage, and an inter-terminal resistance between the firstterminal and the second terminal, a value of an inter-terminal currentbetween the first terminal and the second terminal.

The step of determining the value of the positive load current may alsoinclude determining, using the second voltage and the fourth resistance,a value of a terminal-TIA current from the second terminal to the secondTIA.

The value of the inter-terminal current value and the value of theterminal-TIA current value may be utilized to determine the value of thepositive load current. The value of the negative load current may bedetermined utilizing steps similar to steps utilized in determining thevalue of the positive load current.

Two or more ratios of resistances associated with the TIAs may beconfigured to equal, to simplify implementation. Two or more of theresistances across TIAs also may be configured to be equal forsimplifying implementation.

The method may also include controlling at least a first ESC voltage atthe positive terminal and a second ESC voltage at the negative terminalusing at least one of the second voltage and the fourth voltage. Themethod may also include control the difference between the first ESCvoltage and the second ESC voltage using at least one of the secondvoltage and the fourth voltage.

The features and advantages of the present invention may be betterunderstood with reference to the figures and discussions that follow.

FIG. 2A illustrates a schematic representation of an arrangement formeasuring a value/amperage I_(LP) of a positive load current 215 appliedto a positive terminal of an electrostatic chuck in a plasma processingsystem (similar to plasma processing system 160 illustrated in theexample of FIG. 1A) in accordance with one or more embodiments of theinvention.

The plasma processing system may include a power supply, such as a DCpower supply similar to DC power supply 166 illustrated in the exampleof FIG. 1A. The power supply may be configured to supply a positive highvoltage (+HV) 299 to a positive terminal (similar to positive terminal185 illustrated in the example of FIG. 1A) of an electrostatic chuck(similar to chuck 164 illustrated in the example of FIG. 1A) inside aplasma processing chamber (similar to plasma processing chamber 169illustrated in the example of FIG. 1A) of the plasma processing systemthrough a RF filter (similar to RF filter 167 illustrated in the exampleof FIG. 1A). The resistance of the positive terminal and the RF filtermay be represented by an equivalent resistor 217.

In one or more embodiments, a clamp voltage 271, i.e., the differencebetween positive high voltage (+HV) 299 and a corresponding negativehigh voltage (−HV) 399 (also illustrated in the example of FIG. 3)supplied by the power supply may be in excess of 6 kV. For example,positive high voltage (+HV) 299 may be about +4.5 kV, and thecorresponding negative high voltage (−HV) 399 may be about −1.5 kV. Inanother example, positive high voltage (+HV) 299 may be about +1.5 kV,and the corresponding negative high voltage (−HV) 399 may be about −4.5kV. A bias voltage 270, a center point of clamp voltage 271 (betweenpositive high voltage (+HV) 299 and negative high voltage (−HV) 399),may be tuned to match a plasma induced bias voltage 294.

The plasma processing system may also include a first trans-impedanceamplifier 210 (TIA 210) electrically connected to a first terminal 251positioned on the electrical path (or power supply path) between thepower supply and the positive terminal. First TIA 210 may be coupledwith first terminal 251 through a first component/resistor 205 a with afirst resistance value RD₁. A second component/resistor 209 a with asecond resistance value RD₂ may be implemented across two ends of firstTIA 210. The ratio of RD₁ to RD₂ may be chosen for simplifyingmeasurement of positive load current 215. As an example, the ratio ofRD₁ to RD₂ may be configured to be 600.

The plasma processing system may also include a second TIA 208electrically connected to a second terminal 252 on the power supply paththrough a third component/resistor 205 b also with the first resistancevalue RD₁. In one or more embodiments, third component/resistor 205 bmay have a different resistance value (other than RD₁). A fourthcomponent/resistor 209 b also with the second resistance value RD₂ maybe implemented across two endpoints of TIA 208. In one or moreembodiments, fourth component/resistor 209 b may have a differentresistance value (other than RD₂).

FIG. 2B illustrates a flowchart of a method for obtaining thevalue/amperage I_(LP) of positive load current 215 in accordance withone or more embodiments of the present invention. Positive load current215 may represent the current supplied to the positive terminal of theelectrostatic chuck in the plasma processing chamber of the plasmaprocessing system.

Referring to FIG. 2A-B, the process may start with step 272, in whichsecond TIA 208 may measure voltage VD₂ across component 209 b (with aspecified resistance value RD₂). Accordingly, voltage V₂ at secondterminal 252 may be calculated utilizing VD₂ and the ratio of the ratioof RD₁ to RD₂. In the example where RD₁/RD₂=600, V₂ may be calculatedutilizing V₂=−VD₂*600. V₂ may also represent the voltage at the positiveterminal (+ESC) of the ESC. V₂ may be positive. V₂ may also be negativewhen polarities of the positive terminal and the negative terminals arereversed.

Similarly, TIA 210 may measure VD₁ across component 209 a. At firstterminal 251, voltage V₁ (which may represent the value of positive highvoltage 299) may be calculated utilizing VD₁ and the ratio of the ratioof RD₁ to RD₁. In the example where RD₁/RD₂=600, V₁ may be calculatedutilizing V₁=−VD₁*600.

In step 274, voltage V₁₂ across sensing resistor 250 (with a resistancevalue R_(S)) between first terminal 251 and second terminal 252 may bedetermined by subtracting V₂ from V₁ 229, i.e., V₁₂=V₁−V₂.

In step 276, the current amount/amperage I_(SP) of a current 204 acrosssensing resistor 250 may be determined with V₁₂ divided by R_(S), i.e.,I_(SP)−V₁₂/R_(S).

In step 278, the current amount/amperage I_(q2P) of a current 206 fromsecond terminal 252 to second TIA 208 may be determined with VD₂ dividedby RD₂, i.e., I_(q2P)=VD₂/RD₂.

In step 280, the current amount/amperage I_(q2P) of positive loadcurrent 215 may be determined by subtracting I_(q2P) from I_(SP), i.e.,I_(SP)−I_(q2P).

An arrangement similar to the arrangement illustrated in the example ofFIG. 2A may be implemented for obtaining the value of the negative loadcurrent associated with negative high voltage 399 in the plasmaprocessing system. A method similar to the method illustrated in theexample of FIG. 2B may be implemented for obtaining the value of thenegative load current.

FIG. 2C illustrates a mathematical manipulation for obtaining thevalue/amperage I_(LP) of positive load current 215. As illustrated byequation 241, an intermediate voltage term V_(ISP) may be calculatedutilizing the difference between measured VD₁ and VD₂ and anintermediate term X, i.e., V_(ISP)=(VD₁−VD₂)*(−X).

Subsequently, as illustrated by equation 242, ΔV may be calculatedutilizing another intermediate term Y, intermediate voltage termV_(ISP), VD₂, specified R_(S), and specified RD₂, i.e.,ΔV=(Y)*(V_(ISP))+(VD₂)*(R_(S)/RD₂).

The values of intermediate terms X and Y may be determined based on theratio of RD₁ to RD₂, as well as capability of TIAs and other equipmentutilized for measuring voltage values. In particular, the product ofintermediate terms X and Y pertain to the ratio of ratio of RD₁ to RD₂.In the example where RD₁/RD₂=600, intermediate term X may be −60, andintermediate term Y may be 10, in one or more embodiments. In one ormore embodiments, intermediate term X may be −30, and intermediate termY may be 20.

As illustrated by equation 243, the value I_(LP) of positive loadcurrent 215 may be calculated with ΔV divided by R_(S), i.e.,I_(LP)=(ΔV)/(R_(S)).

Advantageously, the RD₁/RD₂ ratio may be reduced into smallerintermediate terms X and Y, such that the voltage values according toembodiments of the invention may be conveniently measured. For example,the voltage values involved in embodiments of the invention may be tunedto fall within optimal operating ranges of TIAs utilized by adjustingthe values of intermediate terms X and Y.

FIG. 3 illustrates a schematic representation of an arrangement forobtaining a value/amperage I_(LN) of a negative load current 315 appliedto a negative terminal of the electrostatic chuck in the plasmaprocessing system discussed in the example of FIG. 2A-C in accordancewith one or more embodiments of the present invention. The power supplymay be configured to supply a negative high voltage 399 to a negativeterminal of the electrostatic chuck inside the plasma processing chamberof the plasma processing system through a RF filter. The resistance ofthe negative terminal and the RF filter may be represented by anequivalent resistor 317.

The plasma processing system may further include a third TIA 310 and afourth TIA 308 configured to provide measurement of voltages forcalculating the value I_(SN) of sensing current 314 across sensingresistance 350. Fourth TIA 308 may also be configured to provide voltagemeasurement for calculating the value/amperage I_(q2N) of current 306from a second terminal 352 to fourth TIA 308 across component/resistor305 b. Accordingly, I_(LN) may be calculated utilizing I_(SN) andI_(q2N). The arrangement illustrated in the example of FIG. 3 may besimilar to the arrangement illustrated in the example of FIG. 2A, andthe methods of utilizing the arrangement illustrated in the example ofFIG. 3 may be similar to the methods illustrated in the examples of FIG.2B-C.

The plasma processing system may further include a clamp control unit.The clamp control unit may be configured to control at least one of afirst ESC voltage V₂ at the positive terminal (+ESC) and a second ESCvoltage V₄ at the negative terminal (−ESC) using at least one of VD₂measured by second TIA 208 and VD₄ measured by fourth TIA 308. Aspreviously discussed, V₂ may be proportional to VD₂. Similarly, V₄ maybe proportional to VD₄. In particular, the clamp control unit maycontrol the difference between V₂ and V₄. The difference between V₂ andV₄ may also be considered a clamp voltage pertaining to the clampingforces applied to the wafer supported by the ESC.

FIG. 4 illustrates a positive load current plot 406 and a negative loadcurrent plot 408 for optimizing a bias voltage in the plasma processingsystem discussed in FIGS. 2A-C and 3 in accordance with one or moreembodiments of the present invention. As illustrated in the example ofFIG. 4, in a plasma processing system, a decrease of plasma induced biasvoltage 294 (relative to a bias voltage 402 optimized for securing awafer on an electrostatic chuck) may correspond to an increase in thepositive load current and may correspond to a decrease in the negativeload current. The value of the positive load current may be obtainedutilizing one or more of the arrangements and/or methods according toone or more embodiments of the present invention as illustrated in theexamples of FIGS. 2A-C. The value of the negative load current may beobtained utilizing one or more arrangements and/or methods according toone or more embodiments of the present invention as illustrated in oneor more of the example of FIG. 3 and/or similar to one or morearrangements and/or methods illustrated in the examples of FIGS. 2A-C.

In order to stably secure, or “clamp,” a wafer on the electrostaticchuck, substantially equal, balanced forces may need to be applied bythe positive and negative terminals of the chuck. In order to maintainsubstantially equal, balanced forces provided by the positive andnegative terminals of the chuck, the values of the positive load currentand the negative load current may need to be maintained substantiallyequal.

In one or more embodiments of the invention, bias voltage 402 may betuned (e.g., programmed and/or configured in a power supply, e.g.,utilizing an automatic control program in a control unit similar to biascontrol or sensor input 198) such that the values of the positive loadcurrent and the negative load current may be substantially equal, asillustrated by cross point 405 of positive load current plot 406 andnegative load current plot 408 in the example of FIG. 4. In the exampleof FIG. 4, the value of bias voltage 402 to provide a secure andbalanced clamp of the wafer may be around −800 V, which corresponds toamperage of about 6.6*10⁻⁶ A for both the positive load current and thenegative load current.

In one or more embodiments, the amperage of the positive load currentand/or the negative load current obtained may be utilized in determiningthe health condition and/or the life expectancy of the electrostaticchuck.

As can be appreciated from the foregoing, embodiments of the inventionmay provide amperage/values of the positive load current and thenegative load current in a plasma processing system without requiring anexpensive isolation amplifier. Advantageously, the cost associated withobtaining the values may be reduced.

Further, without depending on an isolation amplifier and instrumentationamplifier, embodiments of the invention may be able to provide values ofpositive load currents and negative load currents in plasma processingsystems that operate at voltage levels that are beyond the capability ofa typical isolation amplifier (and a typical instrumentation amplifier,which may only be operable within a limited range, such as −10V˜+10V).Utilizing TIAs, high voltages may be scaled down by implementing highresistance between the power supply path and the TIA. Further,intermediate voltage and intermediate terms may be employed to enablemeasurement to be performed in the optimal ranges of TIAs. Therefore,embodiments of the invention may be especially useful for very highvoltage plasma processing systems.

Embodiments of the invention also take into account the current flowingfrom a terminal on the power supply path to the TIA. Advantageously,embodiments of the invention may provide more accurate values of loadcurrents, thereby providing more accurate control of bias voltage forsecuring a wafer on an electrostatic chuck. Advantageously, embodimentsof the invention may produce higher yield in plasma processing.

While this invention has been described in terms of several embodiments,there are alterations, permutations, and equivalents, which fall withinthe scope of this invention. It should also be noted that there are manyalternative ways of implementing the methods and apparatuses of thepresent invention. Furthermore, embodiments of the present invention mayfind utility in other applications. The abstract section may be providedherein for convenience and, due to word count limitation, may beaccordingly written for reading convenience and should not be employedto limit the scope of the claims. It may be therefore intended that thefollowing appended claims be interpreted as including all suchalternations, permutations, and equivalents as fall within the truespirit and scope of the present invention.

1. A plasma processing system for processing a wafer, the plasmaprocessing system comprising: an electrostatic chuck (ESC) positionedinside a plasma processing chamber and configured to support the wafer,the ESC including a positive terminal for providing a first force to thewafer and a negative terminal for providing a second force to the wafer;a first trans-impedance amplifier (TIA) and a second TIA configured tomeasure a first set of voltages for determining a value of a positiveload current applied to the positive terminal; a third TIA and a fourthTIA configured to measure a second set of voltages for determining avalue of a negative load current applied to the negative terminal; and aprogram configured to adjust a bias voltage using the value of thepositive load current and the value of the negative load current forbalancing the first force and the second force.
 2. The plasma processingsystem of claim 1 wherein the bias voltage is adjusted to produce anoffset between a magnitude of the positive load current and a magnitudeof the negative load current, and the offset is used for correcting anerror of an estimated plasma induced bias voltage.
 3. The plasmaprocessing system of claim 1 further comprising a diagnostic unitconfigured to determine at least one of a health condition and aremaining life of the ESC based on at least one of the value of thepositive load current and the value of the negative load current.
 4. Theplasma processing system of claim 1 further comprising: a firstcomponent configured to connect the first TIA to a first electricalpath, the first electrical path being between a power supply and thepositive terminal, the first component having a first resistance; asecond component connecting two end points of the first TIA, the secondcomponent having a second resistance; a third component configured toconnect the second TIA to the first electrical path, the third componenthaving a third resistance; and a fourth component connecting two endpoints of the second TIA, the fourth component having a fourthresistance, wherein a ratio of the third resistance to the fourthresistance is equal to a ratio of the first resistance to the secondresistance.
 5. The plasma processing system of claim 4 wherein the thirdresistance is equal to the first resistance.
 6. The plasma processingsystem of claim 4 wherein the first set of voltages includes a voltageacross the second component and a voltage across the fourth component.7. The plasma processing system of claim 4 further comprising: a fifthcomponent configured to connect the third TIA to a second electricalpath, the second electrical path being between the power supply and thenegative terminal, the fifth component having a fifth resistance; asixth component connecting two end points of the third TIA, the sixthcomponent having a sixth resistance; a seventh component configured toconnect the fourth TIA to the second electrical path, the seventhcomponent having a seventh resistance; and a eighth component connectingtwo end points of the fourth TIA, the eighth component having a eighthresistance, wherein a ratio of the seventh resistance to the eighthresistance is equal to a ratio of the fifth resistance to the sixthresistance.
 8. The plasma processing system of claim 7 wherein theseventh resistance is equal to the fifth resistance.
 9. The plasmaprocessing system of claim 7 wherein a ratio of the first resistance tothe second resistance is equal to a ratio of the fifth resistance to thesixth resistance.
 10. The plasma processing system of claim 7 whereinthe second set of voltages includes a voltage across the sixth componentand a voltage across the eighth component.
 11. The plasma processingsystem of claim 1 further comprising a resistor disposed between a firstterminal and a second terminal on an electrical path between a powersupply and the positive terminal, wherein the first TIA is connected tothe electrical path at the first terminal, and the second TIA isconnected to the electrical path at the second terminal.
 12. The plasmaprocessing system of claim 1 further comprising a control unitconfigured to control at least a first ESC voltage at the positiveterminal and a second ESC voltage at the negative terminal using atleast one of a first voltage measured by the second TIA and a secondvoltage measured by the fourth TIA, the first ESC voltage beingproportional to the first voltage, the second ESC voltage beingproportional to the second voltage.
 13. The plasma processing system ofclaim 1 further comprising a control unit configured to control adifference between a first ESC voltage at the positive terminal and asecond ESC voltage at the negative terminal using at least one of afirst voltage measured by the second TIA and a second voltage measuredby the fourth TIA, the first ESC voltage being proportional to the firstvoltage, the second ESC voltage being proportional to the secondvoltage.
 14. A method for securing a wafer on an electrostatic chuck(ESC) inside a plasma processing chamber, the ESC including a positiveterminal for providing a first force to the wafer and a negativeterminal for providing a second force to the wafer, the methodcomprising: connecting, using a first component, a first trans-impedanceamplifier (TIA) to a first terminal on a first electrical path, thefirst electrical path being between a power supply and the positiveterminal, the first component having a first resistance; determining,using the first TIA, a first voltage across a second component, thesecond component connecting two end points of the first TIA and having asecond resistance; connecting, using a third component, a second TIA toa second terminal on the first electrical path, the third componenthaving a third resistance; determining, using the second TIA, a secondvoltage across a fourth component, the fourth component connecting twoend points of the second TIA and having a fourth resistance; determininga value of a positive load current applied to the positive terminalusing one or more of the first voltage, the first resistance, the secondresistance, the second voltage, the third resistance, and the fourthresistance; determining a value of a negative load current applied tothe negative terminal; and adjusting a bias voltage using the value ofthe positive load current and the value of the negative load current forbalancing the first force and the second force.
 15. The method of claim14 wherein the bias voltage is adjusted to produce an offset between amagnitude of the positive load current and a magnitude of the negativeload current, and the offset is used for correcting an error of anestimated plasma induced bias voltage.
 16. The method of claim 14further comprising configuring the first resistance, the secondresistance, the third resistance, and the fourth resistance such that aratio of the first resistance to the second resistance is equal to aratio of the third resistance to the fourth resistance.
 17. The methodof claim 14 further comprising configuring the first resistance, thesecond resistance, the third resistance, and the fourth resistance suchthat a the first resistance is equal to the third resistance and thatthe second resistance is equal the fourth resistance.
 18. The method ofclaim 14 further comprising converting a ratio of the first resistanceto the second resistance into a product of at least a first intermediateterm and a second intermediate term.
 19. The method of claim 18 furthercomprising calculating an intermediate voltage term using the firstvoltage, the second voltage, and the first intermediate term.
 20. Themethod of claim 19 further comprising calculating an inter-terminalvoltage between the first terminal and the second terminal using theintermediate voltage term, the second intermediate term, the secondvoltage, the second resistance, and an inter-terminal resistance betweenthe first terminal and the second terminal.
 21. The method of claim 14wherein the determining the value of the positive load current includesdetermining, using the first voltage, the first resistance, and thesecond resistance, a first terminal voltage at the first terminal;determining, using the second voltage, the third resistance, and thefourth resistance, a second terminal voltage at the second terminal;determining, using the first terminal voltage, the second terminalvoltage, and an inter-terminal resistance between the first terminal andthe second terminal, a value of an inter-terminal current between thefirst terminal and the second terminal; determining, using the secondvoltage and the fourth resistance, a value of a terminal-TIA currentfrom the second terminal to the second TIA; and determining, using thevalue of the inter-terminal current value and the value of theterminal-TIA current value, the value of the positive load current. 22.The method of claim 21 wherein the determining the first terminalvoltage includes using the ratio of the first resistance to the secondresistance.
 23. The method of claim 14 wherein the determining the valueof the negative load current includes connecting, using a fifthcomponent, a third TIA to a third terminal on a second electrical path,the second electrical path being between the power supply and thenegative terminal, the fifth component having a fifth resistance;determining, using the third TIA, a third voltage across a sixthcomponent, the sixth component connecting two end points of the thirdTIA and having a sixth resistance; connecting, using a seventhcomponent, a fourth TIA to a fourth terminal on the second electricalpath, the seventh component having a seventh resistance; determining,using the fourth TIA, a fourth voltage across an eighth component, theeighth component connecting two end points of the fourth TIA, the eighthcomponent having a eighth resistance; and determining the value of thenegative load current using one or more of the third voltage, the fifthresistance, the sixth resistance, the fourth voltage, the seventhresistance, and the eighth resistance.
 24. The method of claim 23wherein the determining the value of the negative load current furtherincludes determining, using the third voltage, the fifth resistance, andthe sixth resistance, a third terminal voltage at the third terminal;determining, using the fourth voltage, the seventh resistance, and theeighth resistance, a fourth terminal voltage at the fourth terminal;determining, using the third terminal voltage, the fourth terminalvoltage, and a second inter-terminal resistance between the thirdterminal and the fourth terminal, a value of a second inter-terminalcurrent between the third terminal and the fourth terminal; determining,using the fourth voltage and the eighth resistance, a value of a secondterminal-TIA current from the fourth terminal to the fourth TIA; anddetermining, using the value of the second inter-terminal current valueand the value of the second terminal-TIA current, the value of thenegative load current.
 25. The method of claim 23 further comprisingconfiguring the fifth resistance, the sixth resistance, the seventhresistance, and the eighth resistance such that a ratio of the fifthresistance to the sixth resistance is equal to a ratio of the seventhresistance to the eighth resistance.
 26. The method of claim 23 furthercomprising: converting a ratio of the fifth resistance to the sixthresistance into a product of at least a third intermediate term and afourth intermediate term; calculating a second intermediate voltage termusing the third voltage, the fourth voltage, and the third intermediateterm; and calculating a second inter-terminal voltage between the thirdterminal and the fourth terminal using the second intermediate voltageterm, the fourth intermediate term, the fourth voltage, the fourthresistance, and a second inter-terminal resistance between the thirdterminal and the fourth terminal.
 27. The method of claim 23 furthercomprising controlling at least a first ESC voltage at the positiveterminal and a second ESC voltage at the negative terminal using atleast one of the second voltage and the fourth voltage, the first ESCvoltage being proportional to the second voltage, the second ESC voltagebeing proportional to the fourth voltage.
 28. The method of claim 23further comprising controlling a difference between a first ESC voltageat the positive terminal and a second ESC voltage at the negativeterminal using at least one of the second voltage and the fourthvoltage, the first ESC voltage being proportional to the second voltage,the second ESC voltage being proportional to the fourth voltage.
 29. Themethod of claim 14 further comprising determining at least one of ahealth condition and a remaining life of the ESC based on at least oneof the value of the positive load current and the value of the negativeload current.